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Session
64
: Backplane Technologies for Display Manufacturing |
Display Manufacturing
|
Thursday, May 16 / 10:40 AM - 12:20 PM / San Jose Convention Center, LL20A
Chair:
Sangyeol Kim, Samsung Display, Yongin, South Korea
Co-Chair:
Toshiaki Arai, Japan Display.Inc., Ebina-shi, Japan
64.1 - Protrusion-Free LTPS Using the CMP Process and Its OLED Application (10:40 AM - 11:00 AM)
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Woojin Cho
Samsung Display Co., Ltd. Yongin South Korea
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Low-temperature polysilicon (LTPS) is the most popular channel material used in the thin-film transistor. It has protrusions due to the volume expansion of Si and the presence of its native oxide. The protrusions cause negative effects such as interface trap, hysteresis, and so on. In that sense, the heights need to be lowered or eventually flattened. In this study, the authors use the chemical mechanical planarization (CMP) technique to reduce the surface roughness of LTPS to 1 nm and even lower. They prepare an AMOLED panel with reduced gate insulator thickness by using the CMP process, and this shows less hysteresis.
64.2 - Effect of Polysilicon Grain Boundary Reduction on LTPS Devices and Display Effects Applied to Flexible AMOLED (11:00 AM - 11:20 AM)
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Bing Meng, Huanhuan Zhang, Wangfeng Xi, Min Zhang, Junfeng Li, Rubo Xing, Jianbo Tang
YunGu(Gu'an) Technology Co.,Ltd. Hebei China
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Ying Shen, Edward Lee, Xiujian Zhu, Weiqi Xu
Hefei Visionox Technology Co.,Ltd. Anhui China
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Low-temperature polycrystalline silicon (LTPS) thin-film transisitor devices can be used as core components of pixel driving circuits for active-matrix organic light-emitting displays (AMOLEDs). Polysilicon (P-Si) film and device performance directly affect the display. This paper investigates polysilicon grain boundary reduction for LTPS devices on PI substrates, exploring the effects of grain boundary reduction on LTPS devices and image sticking. Reduction of polysilicon grain boundaries through optimization of the a-Si deposition process, a-Si two-step deposition, an excimer laser annealing (ELA) double-scan process, and the ELA double-scan process reduce grain boundaries by 67%. The authors prepare LTPS devices with thinner gate interlayers (GIs) based on P-Si grain boundary reduction, LTPS devices with positive threshold voltage bias and increased mobility, and AMOLED displays with thinner GIs, which can have 23% better image sticking.
64.3 - Laser Crystallization of Amorphous Silicon via Spot-Beam Annealing Method (11:20 AM - 11:40 AM)
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Won Hee Han, Gi Hyeon Baek
APS Corporation Hwaseong South Korea
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Jin Nyoung Jang
APS Research Corporation Hwaseong South Korea
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Jayoung Park, James Im
Columbia University New York NY US
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kook chul Moon
Sungkyunkwan University Suwon South Korea
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In spot-beam laser annealing, the fiber laser and the polygon scanner-based optical system play a key role by precisely controlling the laser spot position and linear velocities. Key parameters of the laser crystallization are laser power, spot overlap, and line overlap. AFM, Raman, and SEM analyses are used to evaluate polysilicon crystallization states, optimize process parameters, and understand the spot-beam annealing mechanism. This paper presents the spot-beam annealing system configuration and experimental results for low-temperature polysilicon fabrication.
64.4 - ECR Plasma Source for Copper Thin Film Dry Etching (11:40 AM - 12:00 PM)
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JinNyoung Jang, Jong Hwa Jang, Chiwoo Kim
APS Research Hwasung South Korea
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Sangheon Lee, Kiro Jung
APS Inc. Hwasung South Korea
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Donghoon Kim, MunPyo Hong
Korea University Sejong South Korea
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Sang-Gab Kim
Samsung Display Yongin South Korea
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Soo Ouk Jang
Korea institute of Fusion Energy Gunsan South Korea
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A dry-etching process of thin copper films using a high electron temperature electron cyclotron resonance (ECR) plasma source is developed. With the ECR source and reactive ion etching (RIE) mode, an etching rate of 175 nm/min is achieved. Dry etching is performed under high electron temperature plasma source with low temperature substrate and employing a reactive ion-etching mode. To compensate the large-area etching uniformity, a scanning low temperature susceptor is adopted. A rectangular-type microwave slot antenna (ReSLAN) is used to generate ECR plasma.
64.5 - Virtual ESD Failure Detection Methodology for Oxide TFT-Based OLED Panels (12:00 PM - 12:20 PM)
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Hyun Sung Park, Hyeseok Na, Dongjin Seo, Sooyoung Park, Hyeondo Park, Young-Gu Kang, Yujin Choi, Minji Kim, Yudeok Seo, Sung-Chan Jo
Samsung Display Yongin South Korea
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As screen sizes and pixel resolutions increase, electrostatic discharging (ESD) problems have become the most detrimental issue for next-level OLED devices such as IT-OLED, and QD-OLED. In this work, the authors analyze five different types of temporal charging injection mechanisms and three types of failure phenomena. To simulate the multi-scale time-dependent full-panel ESD models, they develop a simplified OLED panel design verification model by using advanced numerical techniques such as perfect boundary approximation and thin sheet-metal approximation. Based on the newly developed simulation methodology, robust OLED panel designs are suggested and experimentally verified.